CAComputer Architecture · Lesson 3 of 7
The Memory Hierarchy & Caches
RAM is ~200 cycles away from the CPU. That's an eternity when you execute 4 instructions per cycle — so CPUs keep copies of recently-used memory in caches. Cache behavior explains more real-world performance than algorithmic complexity does.
Caches work because of locality. Temporal locality: memory you just used, you'll likely use again. Spatial locality: memory near what you just used, you'll likely use next. Caches exploit the second by loading memory in 64-byte cache lines — touch one byte and the surrounding 64 arrive for free. Code that walks memory in order rides this; code that jumps around fights it.
✦ Tip
This is why arrays usually crush linked lists in practice even when big-O says they're equal: array elements are adjacent (cache lines full of useful data), list nodes are scattered (every next-pointer a likely cache miss). Data layout is a first-class performance decision.
This is why arrays usually crush linked lists in practice even when big-O says they're equal: array elements are adjacent (cache lines full of useful data), list nodes are scattered (every next-pointer a likely cache miss). Data layout is a first-class performance decision.
◆ Note
Virtual memory: each process sees its own private address space; hardware (the MMU, using page tables) translates virtual addresses to physical RAM in 4KB pages. This gives isolation (one program can't read another's memory), and lets the OS swap unused pages to disk. A 'segmentation fault' is the MMU catching an access to a page you don't own.
Virtual memory: each process sees its own private address space; hardware (the MMU, using page tables) translates virtual addresses to physical RAM in 4KB pages. This gives isolation (one program can't read another's memory), and lets the OS swap unused pages to disk. A 'segmentation fault' is the MMU catching an access to a page you don't own.